Anybus M40 module setup problems on SPI

fpga-linux

#1

Hello,
Preamble:
I am trying to run M40 module under linux. The platform is Altera Arria 10 soc. Little Endian, Kernel version 4.9.79. I succeeded to map the device to use spidev driver and after many FPGA configurations I have communication in both directions in full duplex mode. Compiled the Generic example with all adaptations needed (according to documents), module is identified, detected. SPI @ 10MHz -3 wire mode, GDB attached to eclipse debugging is used on target debugging.

Target:
To provide a library/kernel module to a SW developers for an application which will use Anybus module for industrial networks

The problem:
I see the ANB: ABP_ANB_STATE_SETUP always. After debugging I saw the checksum at Rx part of the driver is always different and it always retransmit the frame.
What am I missing or any suggestions are welcome.

Cordially
Georgi


#3

Hello Georgi,

Sorry for the delay in getting back to you. We just celebrated a holiday here in the states.

The issue that you have is likely a CRC32 calculation error. However, it could possibly be related to how the CRC is copied to/from the SPI frame. This error will cause the retransmissions, and keep the Anybus state machine in SETUP state.
I recommend that you test your CRC generation function and ensure it is working. Appendix H of the Software design guide has several example arrays and their corresponding CRCs.
One issue that has come up with other customers is that the CRC calculation function has local variables that are of type UINT16 which, by default, is defined to be unsigned short. The issue was for their system shorts had a size that was not 16 bits. Please check the UNIT16 typedef for your target.


#5

Solved:
The SPI speed appeared too high. It works @ 5MHz.


#6

Hello Ian,
Thank you for your response. I posted already but it is not approved maybe that I succeeded to run the Generic part of the software. In our case complications come from that we have a platform device. FPGA + CPU…Not CPU + FPGA. We are facing issues with SPI operation. I decreased the clock and it ran successfully. Anyway it is out of my scope, I am system software guy. So just one another question. Do you have a sources in a project without application part. this will help me, because the application SW people expect from me a library with all the host APIs available for them. If you don’t it is OK :slight_smile: